Abstract

Xilinx System Generator is a Matlab/Simulink high-level based design tool especially for the development of complex digital circuits using Hardware Description Language (HDL). In this paper we propose a high level model for the deblocking filter used in H.264/AVC using System Generator of Matlab/Simulink. Synthesis results are compared with implementations realized using RTL level. The proposed model allows for rapid edits of the architectures and permits the implementation of filters used in other standards and norms (HEVC for example). The proposed implementations are verified using Xilinx-Virtex5 platforms.

Information

Item Type:	Conference
Divisions:
ePrint ID:	636
Date Deposited:	2017-01-15
Further Information:	Google Scholar
URI:	https://www.univ-soukahras.dz/en/publication/article/636

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